View XILINXINC-XQ18V04VQG44N_7485103.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ds125 (v1.0) december 16, 2003 www.xilinx.com 1 advance product specification 1-800-255-7778 ? 2001 ? 2003 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as l isted at http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. features operating temperature range: ?55 c to +125 c low-power advanced cmos flash process memory cells immune to static single event upset in-system programmable 3.3v proms for configuration of xilinx fpgas - endurance of 20,000 program/erase cycles ieee std 1149.1 boundary-scan (jtag) support cascadable for storing longer or multiple bitstreams dual configuration modes - serial slow/fast configuration (up to 20 mhz) - parallel (up to 160 mbps at 20 mhz) 5v tolerant i/o pins accept 5v, 3.3v, and 2.5v signals 3.3v or 2.5v output capability available in plastic vq44 packaging only design support using the xilinx alliance series? and xilinx foundation series? software packages jtag command initiation of standard fpga configuration description xilinx introduces the qpro? xq18v04 military grade 4mbit in-system programmable configuration flash prom (see figure 1 ). the xq18v04 is a 3.3v rewritable prom that provides a reliable non-volatile method for storing large xil- inx fpga configuration bitstreams used in systems that require operation over the full military temperature range. when the fpga is in master serial mode, it generates a configuration clock that drives the prom. a short access time after the rising cclk, data is available on the prom data (d0) pin that is connected to the fpga d in pin. the fpga generates the appropriate number of clock pulses to complete the configuration. when the fpga is in slave serial mode, the prom and the fpga are clocked by an external clock. when the fpga is in selectmap mode (slave), an external oscillator will generate the configuration clock that drives the prom and the fpga. after the rising cclk edge, data is available on the proms data (d0-d7) pins. the data will be clocked into the fpga on the following rising edge of the cclk. see figure 3 . multiple devices can be cascaded by using the ceo output to drive the ce input of the following device. the clock inputs and the data outputs of all proms in this chain are interconnected. the xq18v04 is compatible and can be cascaded with other configuration proms such as the xqr1701l and xqr17v16 one-time programmable config- uration proms. 0 qpro xq18v04 military 4mbit isp configuration flash prom ds125 (v1.0) december 16, 2003 05 advance product specification r figure 1: xq18v04 series block diagram control and jtag interface memory serial or parallel interface d0 data (serial or parallel [express/selectmap] mode) d[1:7] express mode and selectmap interface data address clk ce tck tms tdi tdo oe/reset ceo data ds026_01_021000 7 cf
qpro xq18v04 military 4mbit isp configuration flash prom 2 www.xilinx.com ds125 (v1.0) december 16, 2003 1-800-255-7778 advance product specification r xilinx fpgas and compatible proms capacity connecting configuration proms when connecting the fpga device with the configuration prom (see figure 3 ): the data output(s) of the prom(s) drives the d in input of the lead fpga device. the master fpga cclk output drives the clk input(s) of the prom(s) in master serial and master selectmap modes. the ceo output of a prom drives the ce input of the next prom in a daisy chain (if any). the oe/reset input of all proms is best driven by the init output of the lead fpga device. this connection ensures that the prom address counter is reset before the start of any (re)configuration, even when a reconfiguration is initiated by a v cc glitch. the prom ce input can be driven from the done pin. the ce input of the first (or only) prom can be driven by the done output of the first fpga device, provided that done is not permanently grounded. ce also can be tied permanently low, but this keeps the data output active and causes an unnecessary supply current of 20 ma maximum. d1-d7 remain in a high-impedance state and can be left unconnected when the prom operates in serial mode. express/selectmap mode is similar to slave serial mode. the data is clocked out of the prom one byte per cclk instead of one bit per cclk cycle. see fpga data sheets for special configuration requirements. initiating fpga configuration the xq18v04 device incorporates a pin named cf that is controllable through the jtag config instruction. execut- ing the config instruction through jtag pulses cf low for 300 to 500 ns, which resets the fpga and initiates con- figuration. the cf pin must be connected to the program pin on the fpga(s) to use this feature. the xilinx impact? software can also issue a jtag con- fig command to initiate fpga configuration through the "load fpga" setting. selecting configuration modes the xq18v04 accommodates serial and parallel methods of configuration. the configuration modes are selectable through a user control register in the xq18v04 device. this control register is accessible through jtag, and is set using the "parallel mode" setting on the xilinx impact software. serial output is the default programming mode. cascading configuration proms for multiple fpgas configured as a serial daisy-chain, or a single fpga requiring larger configuration memories in a serial or selectmap configuration mode, cascaded proms provide additional memory (see figure 2 ). multiple xq18v04 devices can be cascaded by using the ceo out- put to drive the ce input of the downstream device. the clock inputs and the data outputs of all the xq18v04 devices in the chain are interconnected. after the last bit from the first prom is read, the next clock signal to the prom asserts its ceo output low and drives its data line to a high-impedance state. the second prom recognizes the low level on its ce input and enables its data output. see figure 3 . after configuration is complete, the address counters of all cascaded proms are reset if the prom oe/reset pin goes low. table 1: fpga configuration storage requirements device configuration bits xq18v04 proms xqv300 1,751,808 1 xqv600 3,607,968 1 xqv1000 6,127,744 2 xq2v1000 3,752,736 1 xq2v3000 9,594,656 3 xq2v6000 19,759,904 5 table 2: prom storage capacity device configuration bits xq18v04 4,194,304
qpro xq18v04 military 4mbit isp configuration flash prom ds125 (v1.0) december 16, 2003 www.xilinx.com 3 advance product specification 1-800-255-7778 r figure 2: jtag chain for configuring devices in master serial mode 4.7k ** 1 2 3 4 tdo dout tdi tms tck vcc vcc din cclk done init vcc mode pins* xilinx fpga master serial vcc d0 vcco tdi clk tms ce tck ceo oe/reset program tdo tdi tms tck din cclk done init vcc mode pins* xilinx fpga slave serial program cf tdo gnd * for mode pin connections, refer to the appropriate fpga data sheet. ** resistor value is 300 ohms for virtex and virtex-e devices, and 4.7k ohms for all others. xq18v04 cascaded prom tdi tms tck tdo j1 ds026_08_120103 vcc vcco vcco vcc d0 vcco tdi clk tms ce tck ceo oe/reset cf tdo gnd xq18v04 first prom vcc
qpro xq18v04 military 4mbit isp configuration flash prom 4 www.xilinx.com ds125 (v1.0) december 16, 2003 1-800-255-7778 advance product specification r figure 3: (a) master serial mode (b) virtex selectmap mode (c) xq4000xl express mode (dotted lines indicate optional connection) program din cclk init done first prom data ceo clk ce optional slave fpgas with identical configurations vcc fpga (low resets the address pointer) v cc v cco optional daisy-chained fpgas with different configurations oe/reset dout modes* vcco cf program virtex select map busy cs write init d[0:7] cclk done clk virtex select map mode d[0:7] ce oe/reset xq18v04 modes*** nc cf 3.3v external osc ceo 4.7k v cc 4.7k v cc ** ** v cc v cco v cc v cco v cc 4.7k v cc 4.7k v cc 1k i/o* m0 m1 cs1 program xq4000xl dout done init xq18v04 ceo ce oe/reset xq4000xl express mode master serial mode 8 cf clk d[0:7] d[0:7] cclk m0 m1 cs1 program optional daisy-chained xq4000xl dout done init d[0:7] cclk 8 to additional optional daisy-chained devices to additional optional daisy-chained devices external osc i/o* 1k *cs and write must be pulled down to be used as i/o. one option is shown. ** resistor value is 300 ohms for virtex and virtex-e devices, and 4.7k ohms for all others. ***for mode pin connections, refer to the appropriate fpga data sheet. ds082_05_120103 *for mode pin connections, refer to the appropriate fpga data sheet. ** resistor value is 300 ohms for virtex and virtex-e devices, and 4.7k ohms for all others . cascaded prom data clk ce oe/reset cf v cc v cco v cc v cco v cc
qpro xq18v04 military 4mbit isp configuration flash prom ds125 (v1.0) december 16, 2003 www.xilinx.com 5 advance product specification 1-800-255-7778 r 5v tolerant i/os the i/os on each re-programmable prom are fully 5v tol- erant even through the core power supply is 3.3v. this allows 5v cmos signals to connect directly to the prom inputs without damage. in addition, the 3.3v v cc power supply can be applied before or after 5v signals are applied to the i/os. in mixed 5v/3.3v/2.5v systems, the user pins, the core power supply (v cc ), and the output power supply (v cco ) may have power applied in any order. this makes the prom devices immune to power supply sequencing issues. reset activation on power up, oe/reset is held low until the xq18v04 is active (1 ms) and is able to supply data after receiving a cclk pulse from the fpga. oe/reset is connected to an external resistor to pull oe/reset high releasing the fpga init and allowing configuration to begin. oe/reset is held low until the xq18v04 voltage reaches the operat- ing voltage range. if the power drops below 2.0v, the prom will reset. oe/reset polarity is not programma- ble. see figure 4 for power-on requirements. standby mode the prom enters a low-power standby mode whenever ce is asserted high. the output remains in a high-impedance state regardless of the state of the oe input. jtag pins tms, tdi, and tdo can be in a high-impedance state or high. see ta b l e 3 . customer control bits the xq18v04 proms have various control bits accessible by the customer. these can be set after the array has been programmed using ?skip user array? in xilinx impact soft- ware. the impact software can set these bits to enable the optional jtag read security, parallel configuration mode, or cf-->d4 pin function. figure 4: v ccint power-on requirements time (ms) volts 3.6v 3.0v 0v recommended operating range recommended v ccint rise time 1ms 50ms 0ms ds026_10_102303 table 3: truth table for prom control inputs control inputs internal address outputs oe/reset ce data ceo i cc high low if address < tc (1) : increment if address > tc (1) : don?t change active high-z high low active reduced low low held reset high-z high active high high held reset high-z high standby low high held reset high-z high standby notes: 1. tc = terminal count = highest address value. tc + 1 = address 0.
qpro xq18v04 military 4mbit isp configuration flash prom 6 www.xilinx.com ds125 (v1.0) december 16, 2003 1-800-255-7778 advance product specification r in-system programming in-system programmable proms can be programmed indi- vidually, or two or more can be chained together and pro- grammed in-system via the standard 4-pin jtag protocol as shown in figure 5 . in-system programming offers quick and efficient design iterations and eliminates unnecessary pack- age handling or socketing of devices. the xilinx develop- ment system provides the programming data sequence using either xilinx impact software and a download cable, a third-party jtag development system, a jtag-compatible board tester, or a simple microprocessor interface that emu- lates the jtag instruction sequence. the impact software also outputs serial vector format (svf) files for use with any tools that accept svf format and with automatic test equip- ment. all outputs are held in a high-impedance state or held at clamp levels during in-system programming. oe/reset the isp programming algorithm requires issuance of a reset that will cause oe to go low. external programming xilinx reprogrammable proms can also be programmed by the xilinx hw-130, the xilinx multipro, or a third party device programmer. this provides the added flexibility of using pre-programmed devices in board design and boundary-scan manufacturing tools, with an in-system pro- grammable option for future enhancements and design changes. reliability and endurance xilinx in-system programmable products provide a guaran- teed endurance level of 2,000 in-system program/erase cycles and a minimum data retention of ten years. each device meets all functional, performance, and data retention specifications within this endurance limit. design security the xilinx in-system programmable prom devices incorpo- rate advanced data security features to fully protect the pro- gramming data against unauthorized reading. ta b l e 4 shows the security setting available. the read security bit can be set by the user to prevent the internal programming pattern from being read or copied via jtag. when set, it allows device erase. erasing the entire device is the only way to reset the read security bit. ta b l e 4 : data security options default = reset set read allowed program/erase allowed verify allowed read inhibited via jtag program/erase allowed verify inhibited figure 5: in-system programming operation (a) solder device to pcb and (b) program using download cable ds026_02_011100 g n d v cc (a) (b)
qpro xq18v04 military 4mbit isp configuration flash prom ds125 (v1.0) december 16, 2003 www.xilinx.com 7 advance product specification 1-800-255-7778 r ieee 1149.1 boundary scan (jtag) the xq18v04 is fully compliant with the ieee std. 1149.1 boundary scan, also known as jtag. a test access port (tap) and registers are provided to support all required boundary-scan instructions, as well as many of the optional instructions specified by ieee std. 1149.1. in addition, the jtag interface is used to implement in-system program- ming (isp) to facilitate configuration, erasure, and verifica- tion operations on the xq18v04 device. ta b l e 5 lists the required and optional boundary-scan instructions supported in the xq18v04. refer to the ieee std. 1149.1 specification for a complete description of boundary-scan architecture and the required and optional instructions. instruction register the instruction register (ir) for the xq18v04 is eight bits wide and is connected between tdi and tdo during an instruction scan sequence. in preparation for an instruction scan sequence, the instruction register is parallel loaded with a fixed instruction capture pattern. this pattern is shifted out onto tdo (lsb first), while an instruction is shifted into the instruction register from tdi. the detailed composition of the instruction capture pattern is illustrated in figure 6 . the isp status field, ir[4], contains logic "1" if the device is currently in isp mode; otherwise, it will contain logic "0". the security field, ir[3], will contain logic "1" if the device has been programmed with the security option turned on; otherwise, it will contain logic "0". boundary-scan register the boundary-scan register is used to control and observe the state of the device pins during the extest, sample/preload, and clamp instructions. each output pin on the xq18v04 has two register stages that contribute to the boundary-scan register, while each input pin only has one register stage. for each output pin, the register stage nearest to tdi con- trols and observes the output state, and the second stage closest to tdo controls and observes the high-z enable state of the pin. for each input pin, the register stage controls and observes the input state of the pin. identification registers the idcode is a fixed, vendor-assigned value that is used to electrically identify the manufacturer and type of the device being addressed. the idcode register is 32 bits wide. the idcode register can be shifted out for examina- tion by using the idcode instruction. the idcode is avail- able to any other system component via jtag. the idcode register has the following binary format: vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1 where v = the die version number f = the family code (50h for the xq18v04) a = the isp prom product id (26h for the xq18v04) c = the company code (49h for xilinx) note: the lsb of the idcode register is always read as logic "1" as defined by ieee std. 1149.1. table 5: boundary scan instructions boundary-scan command binary code [7:0] description required instructions bypass 11111111 enables bypass sample/ preload 00000001 enables boundary-scan sample/preload operation extest 00000000 enables boundary-scan extest operation optional instructions clamp 11111010 enables boundary-scan clamp operation highz 11111100 all outputs in high-impedance state simultaneously idcode 11111110 enables shifting out 32-bit idcode usercode 11111101 enables shifting out 32-bit usercode xq18v04 specific instructions config 11101110 initiates fpga configuration by pulsing cf pin low ir[7:5] ir[4] ir[3] ir[2] ir[1:0] tdi-> 0 0 0 isp status security 0 0 1 ->tdo notes: 1. ir[1:0] = 01 is specified by ieee std. 1149.1. figure 6: instruction register values loaded into ir as part of an instruction scan sequence
qpro xq18v04 military 4mbit isp configuration flash prom 8 www.xilinx.com ds125 (v1.0) december 16, 2003 1-800-255-7778 advance product specification r ta b l e 6 lists the idcode register values for the xq18v00 devices. the usercode instruction gives access to a 32-bit user programmable scratch pad typically used to supply informa- tion about the device?s programmed contents. by using the usercode instruction, a user-programmable identifica- tion code can be shifted out for examination. this code is loaded into the usercode register during programming of the xq18v04 device. if the device is blank or was not loaded during programming, the usercode register will contain ffffffffh. xq18v04 tap characteristics the xq18v04 device performs both in-system program- ming and ieee 1149.1 boundary-scan (jtag) testing via a single 4-wire test access port (tap). this simplifies system designs and allows standard automatic test equipment to perform both functions. the ac characteristics of the xq18v04 tap are described as follows. tap timing figure 7 shows the timing relationships of the tap signals. these tap timing characteristics are identical for both boundary-scan and isp operations. tap ac parameters ta b l e 7 shows the timing parameters for the tap waveforms shown in figure 7 . table 6: idcodes assigned to xq18v04 devices isp prom idcode xq18v04 05036093h figure 7: test access port timing tck t ckmin t mss tms tdi tdo t msh t dih t dov t dis ds026_04_020300 table 7: test access port timing parameters symbol parameter min max units t ckmin tck minimum clock period 200 - ns t mss tms setup time 10 - ns t msh tms hold time 25 - ns t dis tdi setup time 10 - ns t dih tdi hold time 25 - ns t dov tdo valid delay - 25 ns
qpro xq18v04 military 4mbit isp configuration flash prom ds125 (v1.0) december 16, 2003 www.xilinx.com 9 advance product specification 1-800-255-7778 r absolute maximum ratings (1,2) recommended operating conditions quality and reliability characteristics table 8: absolute maximum ratings symbol description value units v ccint /v cco supply voltage relative to gnd ?0.5 to +4.0 v v in input voltage with respect to gnd ?0.5 to +5.5 v v ts voltage applied to high-z output ?0.5 to +5.5 v t stg storage temperature (ambient) ?65 to +150 c t j junction temperature ceramic +150 c plastic +125 c t sol maximum soldering temperature +220 c notes: 1. maximum dc undershoot below gnd must be limited to either 0.5v or 10 ma, whichever is easier to achieve. during transitions, the device pins may undershoot to ?2.0v or overshoot to +7.0v, provided this overshoot or undershoot lasts less then 10 ns and with the forcing current being limited to 200 ma. 2. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under operating condi tions is not implied. exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. table 9: recommended operating conditions symbol parameter min max units v ccint internal voltage supply (t c = ?55 c to +125 c) ceramic 3.0 3.6 v internal voltage supply (t j = ?55 c to +125 c) plastic 3.0 3.6 v v cco supply voltage for output drivers for 3.3v operation 3.0 3.6 v supply voltage for output drivers for 2.5v operation 2.3 2.7 v v il low-level input voltage 0 0.8 v v ih high-level input voltage 2.0 5.5 v v o output voltage 0 v cco v t vcc v ccint rise time from 0v to nominal voltage 1 150ms notes: 1. at power up, the device requires the v ccint power supply to monotonically rise from 0v to nominal voltage within the specified v ccint rise time. if the power supply cannot meet this requirement, then the device might not perform power-on-reset properly. table 10: reliability characteristics symbol description min max units t dr data retention 10 - years n pe program/erase cycles (endurance) 20,000 - cycles v esd electrostatic discharge (esd) 2,000 - volts
qpro xq18v04 military 4mbit isp configuration flash prom 10 www.xilinx.com ds125 (v1.0) december 16, 2003 1-800-255-7778 advance product specification r dc characteristics over operating conditions table 11: dc characteristics symbol parameter test conditions min max units v oh high-level output voltage for 3.3v outputs i oh = ?4 ma 2.4 - v high-level output voltage for 2.5v outputs i oh = ?500 a 90% v cco -v v ol low-level output voltage for 3.3v outputs i ol = 8 ma - 0.4 v low-level output voltage for 2.5v outputs i ol = 500 a-0.4v i cc supply current, active mode 25 mhz - 50 ma i ccs supply current, standby mode - 20 ma i ilj jtag pins tms, tdi, and tdo v cc = max v in = gnd ?100 - a i il input leakage current v cc = max v in = gnd or v cc ?10 10 a i ih input and output high-z leakage current v cc = max v in = gnd or v cc ?10 10 a c in and c out input and output capacitance v in = gnd f = 1.0 mhz -10pf
qpro xq18v04 military 4mbit isp configuration flash prom ds125 (v1.0) december 16, 2003 www.xilinx.com 11 advance product specification 1-800-255-7778 r . ac characteristics over operating conditions for xq18v04 figure 8: pin-to-pin timing diagram oe/reset ce clk data t ce t oe t lc t sce t hce t hoe t cac t oh t df t oh t hc ds026_06_012000 t cyc table 12: ac timing characteristics for single device symbol description min max units t oe oe/reset to data delay - 10 ns t ce ce to data delay - 20 ns t cac clk to data delay - 20 ns t oh data hold from ce , oe/reset , or clk 0 - ns t df ce or oe/reset to data float delay (2) -25ns t cyc clock periods 50 - ns t lc clk low time (3) 10 - ns t hc clk high time (3) 10 - ns t sce ce setup time to clk (to guarantee proper counting) (3) 25 - ms t hce ce high time (to guarantee proper counting) 2 - s t hoe oe/reset hold time (guarantees counters are reset) 25 - ns notes: 1. ac test load = 50 pf. 2. float delays are measured with 5 pf ac loads. transition is measured at 200 mv from steady state active levels. 3. guaranteed by design, not tested. 4. all ac parameters are measured with v il = 0.0v and v ih = 3.0v. 5. if t hce high < 2 s, t ce = 2 s.
qpro xq18v04 military 4mbit isp configuration flash prom 12 www.xilinx.com ds125 (v1.0) december 16, 2003 1-800-255-7778 advance product specification r ac characteristics over operating conditions when cascading for xq18v04 figure 9: pin-to-pin timing diagram for cascaded devices clk data ce ceo first bit last bit t cdf ds026_07_020300 oe/reset t ock t ooe t oce table 13: ac timing characteristics for cascaded devices symbol description min max units t cdf clk to data float delay (2,3) -25 ns t ock clk to ceo delay (3) -20 ns t oce ce to ceo delay (3) -20 ns t ooe oe/reset to ceo delay (3) -20 ns notes: 1. ac test load = 50 pf. 2. float delays are measured with 5 pf ac loads. transition is measured at 200 mv from steady state active levels. 3. guaranteed by design, not tested. 4. all ac parameters are measured with v il = 0.0v and v ih = 3.0v.
qpro xq18v04 military 4mbit isp configuration flash prom ds125 (v1.0) december 16, 2003 www.xilinx.com 13 advance product specification 1-800-255-7778 r pinout and pin description table 14: pin names and descriptions (pins not listed are ?no connect?) pin name boundary scan order function pin description pin number 44-pin vqfp d0 4 data out d0 is the data output pin to provide data for configuring an fpga in serial mode. 40 3output enable d1 6 data out d0-d7 are the output pins to provide parallel data for configuring a xilinx fpga in express/selectmap mode. d1-d7 remain in highz state and can be left unconnected when the prom operates in serial mode. 29 5output enable d2 2 data out 42 1output enable d3 8 data out 27 7output enable d4 24 data out 9 23 output enable d5 10 data out 25 9output enable d6 17 data out 14 16 output enable d7 14 data out 19 13 output enable clk 0 data in each rising edge on the clk input increments the internal address counter if both ce is low and oe/reset is high. 43 oe/ reset 20 data in when low, this input holds the address counter reset and the data output is in a high-impedance state. this is a bidirectional open-drain pin that is held low while the prom is reset. polarity is not programmable. 13 19 data out 18 output enable ce 15 data in when ce is high, this pin puts the device into standby mode and resets the address counter. the data output pin is in a high-impedance state, and the device is in low-power standby mode. 15
qpro xq18v04 military 4mbit isp configuration flash prom 14 www.xilinx.com ds125 (v1.0) december 16, 2003 1-800-255-7778 advance product specification r cf 22 data out allows jtag config instruction to initiate fpga configuration without powering down fpga. this is an open-drain output that is pulsed low by the jtag config command. 10 21 output enable ceo 13 data out chip enable output (ceo ) is connected to the ce input of the next prom in the chain. this output is low when ce is low and oe/reset input is high, and the internal address counter has been incremented beyond its terminal count (tc) value. ceo returns to high when oe/reset goes low or ce goes high. 21 14 output enable gnd gnd is the ground connection. 6, 18, 28, 41 tms test mode select the state of tms on the rising edge of tck determines the state transitions at the test access port (tap) controller. tms has an internal 50 kohm resistive pull-up on it to provide a logic "1" to the device if the pin is not driven. 5 tck test clock this pin is the jtag test clock. it sequences the tap controller and all the jtag test and programming electronics. 7 tdi test data in this pin is the serial input to all jtag instruction and data registers. tdi has an internal 50 kohm resistive pull-up on it to provide a logic "1" to the system if the pin is not driven. 3 tdo test data out this pin is the serial output for all jtag instruction and data registers. tdo has an internal 50 kohm resistive pull-up on it to provide a logic "1" to the system if the pin is not driven. 31 v ccint positive 3.3v supply voltage for internal logic and input buffers. 17, 35, 38 v cco positive 3.3v or 2.5v supply voltage connected to the output voltage drivers. 8, 16, 26, 36 table 14: pin names and descriptions (pins not listed are ?no connect?) (continued) pin name boundary scan order function pin description pin number 44-pin vqfp
qpro xq18v04 military 4mbit isp configuration flash prom ds125 (v1.0) december 16, 2003 www.xilinx.com 15 advance product specification 1-800-255-7778 r package pin diagrams prom package pinout compatibility ordering information revision history the following table shows the revision history for this document. figure 10: package pinout for the xq18v04vq44 1 2 3 4 5 6 7 8 9 10 11 vq44 top view nc nc tdo nc d1 gnd d3 v d5 nc nc cco nc oe/reset d6 ce v cco vccint* gnd d7 nc ceo nc nc nc tdi nc tms gnd tck v d4 cf nc cco nc clk d2 gnd d0 nc vccint* nc v cco vccint* nc ds082_13_102303 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 *see pin descriptions. table 15: prom-to-prom pinout compatibility for the vqfp44 package vq44 xq18v04 xq17v16 5tms n/c 7 tck n/c 3 tdi n/c 31 tdo n/c 10 cf n/c 24 n/c busy 37 n/c gnd 35 v ccint v pp 8, 16, 26, 36 v cco 1 v cc 1. the xq18v04 supports 2.5-3.3v v cco operation. the xq17v16 only supports 3.3v. xq18v04 vq44 n manufacturing grade device number package type device ordering options device type package grade xq18v04 vq44 44-pin plastic thin quad flat package n military plastic t j = ? 55 c to +125 c date version revision 12/16/03 1.0 first publication of this early access specification.

▲Up To Search▲

Price & Availability of XILINXINC-XQ18V04VQG44N

	To Download XILINXINC-XQ18V04VQG44N Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .